In the case of CBR (Constant Bit Rate) transmissions, a uniform system clock is required throughout the network. For this purpose, a hierarchy is established on the basis of the generation of a central system clock. One of the sides communicating functions as master in respect of the clock, and the other side functions as slave. In the case of a transmission in STM (Synchronous Transfer Mode) systems, the receiver of the slave can recover the clock from the received signal and synchronize the processing of the receiving signal and its own transmitter with this clock. In telecommunications systems, the respectively higher network level is generally master in respect of the lower network level. In the subscriber area, basically the network is the master and the subscriber side is the slave.
CBR transmissions in ATM (Asynchronous Transfer Mode) networks specifically require measures for achieving synchronization between source and sink. This situation occurs for example when voice and video transmissions are made over ATM networks. In the case of transmissions in ATM it is not possible to recover a clock from the received signal. Without specific measures for achieving synchronization of the device to be defined as slave, more malfunctions would occur because of the unavoidable frequency deviation of independent systems. In the case of an excessively low clock frequency of the slave, data congestion occurs in its receiver and a "hole in the data" occurs in the receiver of the master. In the case of an excessively high clock frequency of the slave, a "hole in the data`, occurs in its receiver and "data congestion" occurs in the receiver of the master. Various methods are known for ensuring fault-free CBR transmissions in ATM networks and they are standardized in "I-ETS 300 353 Broadband Integrated Services Digital Network (B-ISDN) Asynchronous Transfer Mode (ATM) Adaptation Layer (AA2) specification type 1".
All known methods have in common that an interworking unit, which has an input for the CBR data stream, is arranged on the transmit side (segmentation) of the master. The interworking unit generates ATM cells by segmentation of the CBR data stream according to AAL1, in accordance with I-ETS 300 353 B-ISDN. The generated ATM cells are output onto a real transmission channel via an output of the interworking unit. The real transmission channel is understood to be the totality of all the transmission link components, converters, multiplexers, switching devices, cross connects, etc. which have to be matched to the transmission path to the receiver of the slave. Because of the asynchronous transmission method, the delay time over the real transmission channel is not constant but rather fluctuates about an average time (DTV--Delay Time Variation). The quasi-constant cell rate at the output of the interworking unit of the master is thus subject to greater or lesser fluctuations at the end of the real transmission channel. For this reason, the reception devices always have an input buffer. The size of the input buffer is to be dimensioned as a function of the expected DTV of the real transmission channel, in such a way that the buffer does not overflow even when there is a minimum interval between arriving cells and there is no idle operation of the input buffer when there is a maximum interval between arriving cells when continuous interrogation, in synchronism with the source clock, takes place at the output of the input buffer. The receive side (reassembling) of an interworking unit is connected to the output of the input buffer. A CBR data stream is reassembled from the ATM cells by the interworking unit according to AAL1 in accordance with I-ETS 300 358 B-ISDN. A clock generated by a time base is fed via a further input to the interworking unit on the receiver side. This clock determines the data rate of the CBR data stream which is made available at the output of the inlerworking unit.
In the known SRTS (Synchronous Residual Time-Stamp) method, an SRTS generator, to which the system clock is fed via an input, is arranged on the master side. The SRTS generator generates a time stamp from the system clock, the residue RTS (Residual Time Stamp) of which is fed via an output to an additional input of the interworking unit of the master. The interworking unit of the master inserts the RTS into the AAL1 overhead of the generated ATM cells. The generation and insertion of the RTS are standardized in I-ETS 300 3S3 B-ISDN. The RTS is the deviation from an expected value which unambiguously describes this deviation with 4 bits (1 bit sign, 3 bits value). Since it is a precondition that the expected value is known to the receiver as "a priori information", the latter can regenerate the time stamp again. From the comparison with the receiver's own time base, an adjustment variable for the time base of the receiver can be derived from this. To this end, an SRTS generator, to which the clock of the time base is fed via an input, is arranged on the receive side, for example. The SRTS generator generates, similarly to the SRTS generator on the master side, the corresponding RTS, which is fed to an input of a desired/actual value comparison, from the freewheeling clock of the time base. The second input of the desired/actual value comparison is connected to an additional output of the interworking unit on the receiver side. The interworking unit on the receiver side extracts the RTS of the master side from the received ATM cells and feeds this RTS to the second input of the desired/actual value comparator. The desired/actual value comparator derives from the comparison of the two input signals an error variable which is fed to a controller. The controller generates from the error variable a correcting variable, which is transferred to the time base so that the time base adjusts its clock in accordance with the correcting variable. A detailed description can be found in "ATM Networks, 3rd edition, pp. 179 et seq; Othmar Kyas, DATACOM Publishing House". The disadvantage of this known method is that both the master side and the receiver side have to be modified in terms of hardware and/or software, which makes the described method very costly.
Furthermore, the ACR (Adaptive Clock Recovery) method, which does not require modification on the master side, is known from I-ETS 300 353 B-ISDN. To this end, the input buffer has an additional output on the receiver side. A control signal, which indicates whether the input buffer is more than half filled is present at this additional output. This control signal is transferred to the input of a controller. The controller generates a correcting variable, which is fed to the time base, from the control signal. The time base then adjusts the clock in accordance with the correcting variable. A disadvantage with this method is that a number of cells in the input buffer have to be occupied and this buffering has an effect on the transmission in the form of a delay time. In the case of a transmission at 64 kbits/s, this means an additional delay of 6 ms per cell.